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Parallelism-High Performance Computing-Grid

Domaine
Parallelism-High Performance Computing-Grid
Domain - extra
Parallel Architecture; Compilation
Année
2013
Starting
10/2013
État
Open
Sujet
Embedded Domain Specific Languages for Hardware Accelerators Programming
Thesis advisor
ETIEMBLE Daniel
Co-advisors
FALCOU Joel
Laboratory
Collaborations
Abstract
The hardware accelerators are now the solution of choice for boosting performances of computing systems. However, the tools for handling those accelerators are lagging behind and lack the abstraction layer required to address all kind of accelerators in an uniform way. This PHD thesis aims at finding a high level system, based on Domain Specific Languages, to provide an uniform API for a large range of accelerators.
Context
The hardware accelerators are becoming more and more wide spread, first with GPUs then now with new architectures like the Xeon Phi or with FPGA based solutions. However if the variety and efficiency of such systems is increasing, the tools for programming such accelerators in a simple way are limited to either vendor specific solutions or to low level APIs. Meanwhile, the software tools for high performance computing are slowly shifting toward Domain Specific solutions in which the abstract information of the application domain drives the underlying code generation and optimization process.
Objectives
The objective of this PhD thesis is to investigate the Domain Specific Language based solutions to provide an unified development framework for hardware accelerators like the Xeon Phi or FPGA based systems. This framework will target a few specific domain areas like image processing, linear algebra or machine learning to be able to find generic abstractions between those domains and a way to translate those abstractions into code generation rule sets. Further, this framework will be integrated into our existing scientific computing library -NT2- and applications will be built in order to assess this framework's efficiency and applicability.
Work program
Extra information
Prerequisite
C++, hardware architectures, parallel programming
Détails
Expected funding
Institutional funding
Status of funding
Expected
Candidates
Utilisateur
joel.falcou
Créé
Mardi 11 juin 2013 16:30:34 CEST
dernière modif.
Mardi 11 juin 2013 16:30:34 CEST

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Ecole Doctorale Informatique Paris-Sud


Directrice
Nicole Bidoit
Assistante
Stéphanie Druetta
Conseiller aux thèses
Dominique Gouyou-Beauchamps

ED 427 - Université Paris-Sud
UFR Sciences Orsay
Bat 650 - aile nord - 417
Tel : 01 69 15 63 19
Fax : 01 69 15 63 87
courriel: ed-info à lri.fr